1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with an improved gate resistance and a method of its manufacture.
2. Description of the Related Art
Gate lengths of semiconductor devices may be scaled down to, say, 100 nm or less to produce highly integrated semiconductor device. Along with this reduction in gate lengths has been a lot of effort to improve the gate resistance. One method is to incorporate conductive polysilicon layers in the gates and form cobalt silicide (CoSi2) layers over the gates.
However, in forming a cobalt silicide layer having low resistance, it is important to provide a large contact area between the cobalt layer and the silicon layer of the gate. To this end, a method of recessing gate spacers on sidewalls of the gate to increase an open area of the gate has been proposed.
In this case, when forming local interconnection lines or interconnection contacts that are aligned over the cobalt silicide layer, bridge defects may occur where a local interconnection or an interconnection contact is accidentally electrically connected to a channel of an underlying silicon substrate.
FIGS. 1 through 5 are schematic cross-sectional views illustrating a method of improving the gate resistance of a conventional semiconductor device.
Referring to FIG. 1, according to a method of manufacturing the conventional semiconductor device, an isolation region 15 is formed in a semiconductor substrate 10, and a gate dielectric layer 21 and a gate 23 are formed on the semiconductor substrate 10. A spacer formed of a silicon oxide layer 31 and a silicon nitride layer 33 is then formed on a sidewall of the gate 23, and the spacer is recessed relative to the gate 23 height in both the cell and peripheral regions of the circuit.
Referring to FIG. 2, a cobalt silicide layer 40 is formed on the surface of the gate 23, and an etch stop layer 50 is formed on the cobalt silicide layer 40, spacer layers 31 and 33, exposed substrate 10, and isolation region 15.
Referring to FIG. 3, an insulating layer 60 is formed on the etch stop layer 50, and through holes 61 and 63 are formed in the insulating layer 60 in the cell region and peripheral region respectively. The first through holes 61 of a cell region are aligned over at least a portion of the cobalt silicide layer 40 for an interconnection contact and a local interconnection. The second through hole 63 of a peripheral region is aligned over the semiconductor substrate 10 for connecting a metal interconnection.
Because of the interposition of the gate structure in the cell region and raised etch stop layer 50 atop it, the depth of the first through holes 61 is generally different from the depth of the second through hole 63. Though a portion 51 of the etch stop layer 50 under the first through hole 61 is exposed, the second through hole 63 may not be open to the etch stop layer 50 so that an insulating portion 65 of layer 60 remains thereunder. While the insulating portion 65 is removed by subsequent etching, the portion 51 of the etch stop layer 50 under the first through hole 61 normally prevents underlying layers from being etched further. However, the portion 51 of the etch stop layer 50 may disappear in some cases during the etch process used to complete the hole 63 down through to the substrate 10.
Referring to FIG. 4, since the spacer is recessed and its height is reduced, the silicon oxide layer 31 of the spacer may be exposed and disappear as the etch process progresses. Furthermore, after completing the etch process for removing the insulating layer 60 for the first and second through holes 61 and 63, a large amount of the silicon oxide layer 31 may disappear during an etch process for removing the exposed etch stop layer 50.
Therefore, most portions of the exposed silicon oxide layer 31 disappear during the etch process for removing the insulating layer 60 and/or the removal of the etch stop layer 50, so that defects may easily occur when a portion of the semiconductor substrate 10 under the silicon oxide layer 31, i.e., a surface of a transistor channel or a junction, is exposed. That is, an undesirable bridge hole 66 may expose the surface of the semiconductor substrate 10 under the first through holes 61.
Referring to FIG. 5, if the hole 66 is undesirably formed, a short between first contact 71 and second contract 73 may form. That is, the first and second through holes 61 and 63 are filled with tungsten or other conductor to form a first contact 71 and a second contact 73. At this time, the first contact 71, which may be the interconnection contact or the local interconnection in the cell region, is extended to the bridge hole 66 so that a bridge 72 may be formed to fill the bridge hole 66. Due to the bridge 72, defects may occur where the first contact 71 and the semiconductor substrate 10 may be accidentally shorted together.
Since the first through hole 61 aligned over the gate 23 is needed in the cell region, it is understood that the bridge 72 is caused by a recess structure of the spacer. Accordingly, there is a great need for developing a method of preventing the bridge 72 in the cell region as well as improving the gate resistance of the semiconductor transistor.